1. Field of the Invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a polysilicon thin film transistor (Poly-Si TFT) and a method of manufacturing the same.
2. Description of Related Art
In order to form a polycrystalline silicon layer as an active layer of the TFT, firstly an intrinsic amorphous silicon layer is first deposited using a plasma chemical vapor deposition (PCVD) technique or a low pressure chemical vapor deposition (LPCVD) technique so that an amorphous silicon layer is formed. Second, the amorphous silicon layer is crystallized through one or a combination of processes that may include a laser annealing technique, a solid phase crystallization (SPC) technique, and a metal induced crystallization (MIC) technique.
FIGS. 1A to 1D are cross-sectional views illustrating a known process of manufacturing a coplanar type polysilicon thin film transistor using a metal induced crystallization technique. As shown in FIG. 1A, a buffer layer 2 and an amorphous silicon layer 4 are deposited sequentially on a substrate 1. The buffer layer 2 serves to prevent the extraction of any alkali material from the substrate 1. A metal layer typically having a thickness of 30.ANG.A is deposited on the amorphous silicon layer 4 using a sputtering technique. Then, the amorphous silicon layer 4 is crystallized through a long duration heat treatment at a temperature of 500.degree. C. to form a polysilicon layer 10.
A gate insulating layer 6 and a gate electrode 8 are formed sequentially on the polysilicon layer 10. The polysilicon layer 10 is patterned in the form of an island that has a width greater than that of both the gate insulating layer 6 and the gate electrode 8.
Susequently, as shown in FIG. 1B, an ion-doping process is carried out to define source and drain regions 12 and 14 using the gate electrode 8 as a mask. At this time, the electrical characteristics of the polysilicon layer 10 depend on a doped impurity gas that is either a p-type impurity gas such as B.sub.2 H.sub.6 or an n-type impurity gas such as PH.sub.3. The polysilicon layer portion 11 serves as an active area. After the ion-doping process, the activation process follows to activate the gas impurity-doped regions.
Next, as shown in FIG. 1C, an interlayer insulator 16 is formed over the whole substrate 1 covering the gate insulating layer 6 and the gate electrode 8. Interlayer insulator 16 is then etched to form contact holes 26 and 28, exposing the source and drain regions 12 and 14, respectively. Then, source and drain electrodes 18 and 20 are formed to contact the source and drain regions 12 and 14 respectively through the contact holes 26 and 28. In other words, source electrode 18 is formed to contact source region 12 through contact hole 26, and drain electrode 20 is formed to contact drain region 14 through contact hole 28. A passivation film 22 is formed over the entire substrate and etched to form a contact hole 30, exposing a portion of the drain electrode 20. A transparent conductive electrode is deposited and patterned into a pixel electrode 24 that contacts the exposed portion of the drain electrode 20 through contact hole 30, thereby completing fabrication of the most important components of the conventional coplanar type Poly-Si TFT.
In the conventional coplanar type Poly-Si TFT described above, however, the active area 11 that is substantially a channel region of the TFT contacts with the metal layer used during the crystallization process, thereby degrading the electrical characteristics of the Poly-Si TFT Besides, since the activation process is an additional production step, the yield can be reduced.
To overcome the above problems, a metal induced lateral crystallization (MILC) technique has been introduced. FIG. 2 is a cross sectional view illustrating a lateral crystallization method. As shown in FIG. 2, the crystallization process of the amorphous silicon layer is not performed as in the FIG. 1A. Instead, an amorphous silicon layer 10' is patterned in the form of an island, and the gate insulating layer 6 and the gate electrode 8 are formed. Then, source and drain regions 12' and 14' are formed by an ion-doping process. A metal layer 3 is formed over the whole substrate 1 covering the gate electrode 8. Subsequently, the amorphous silicon layer 10' is crystallized by a long duration, high temperature treatment to form a polysilicon layer. At this point, crystal grains of the polysilicon layer grow from both end portions of the intrinsic amorphous silicon area 11' to a central portion at the same time that the source and drain regions 12' and 14' are crystallized. Accordingly, since the active area 11' under the gate insulating layer 6 does not contact the metal layer 3, electrical characteristics of the TFT is improved.
However, lateral crystallization of the intrinsic silicon layer requires a lengthy processing time, thereby causing a low yield. Production time is further lengthened by the additional processing step of activation.